Digital Verification Engineer

Provide the basic functions of the website; Allow users to use social media features; Digital Verification Engineer Intern/ Thesis M/F Posting title Digital Verification Engineer Intern/ Thesis M/F Regular/Temporary Temporary Support the activity of digital verification within RFC-DDC verification team using the state of art of verification methodology (e.g. SystemVerilog, UVM, CDCRV, SW Driven Verification, Object Driven verification, Formal verification, scripting) Profile basic of digital design basic of digital verification basic of SW programming basic of scripting languages (sh, csh, python, makefile) knowledge of Verilog and/or Vhdl is considered a plus knowledge of SystemVerilog languages is considered a plus knowledge of Universal Verification Methodology (UVM) is considered a plus Job location Less than 2 years Languages Requester 01/09/2023 General information Reference 2023-33213 Job level 080 – Technical Non-Exempt You may be interested in these vacancies